1. Technical Field of the Invention
This invention relates in general to the field of memory architecture in computer systems, and more specifically to an improved method and apparatus for high availability redundant memory.
2. Background
Computer systems generally consist of one or more processors that execute program instructions stored within a medium. This mass storage medium is most often constructed of the lowest cost per bit, yet slowest storage technology, typically magnetic or optical media. To increase the system performance, a higher speed, yet smaller and more costly memory, known as the main memory, is first loaded with information from the mass storage for more efficient direct access by the processors. Even greater performance is achieved when a higher speed, yet smaller and more costly memory, known as a cache memory, is placed between the processor and main memory to provide temporary storage of recent/and or frequently referenced information. As the difference between processor speed and access time of the final storage increases, more levels of cache memory are provided, each level backing the previous level to form a storage hierarchy. Each level of the cache is managed to maintain the information most useful to the processor.
Often more than one cache memory will be employed at the same hierarchy level, for example when an independent cache is employed for each processor. Caches have evolved into quite varied and sophisticated structures, but always address the tradeoff between speed and both cost and complexity, while functioning to make the most useful information available to the processor as efficiently as possible.
Recently, cost reduced computer system architectures have been developed that more than double the effective size of the main memory by employing high speed compression/decompression hardware based on common compression algorithms, in the path of information flow to and from the main memory. Processor access to main memory within these systems is performed indirectly through the compressor and decompressor apparatuses, both of which add significantly to the processor access latency costs.
Large high speed cache memories are implemented between the processor and the compressor and decompressor hardware to reduce the frequency of processor references to the compressed memory, mitigating the effects of the high compression/decompression latency. These caches are partitioned into cache lines, equal in size to the fixed information block size required by the compressor and decompressor.
Referring to FIG. 1, a block diagram of a prior art computer system 100 is shown. The computer system includes one or more processors 101 connected to a common shared memory controller 102 that provides access to a system main memory 103. The shared memory controller contains a compressor 104 for compressing fixed size information blocks into as small a unit as possible for ultimate storage into the main memory, a decompressor 105 for reversing the compression operation after the stored information is later retrieved from the main memory, and write queue 113 for queuing main memory store request information block(s) destined for the compressor. The processor data bus 108 is used for transporting uncompressed information between other processors and/or the shared memory controller. Information may be transferred to the processor data bus 108 from the main memory 103, either through or around the decompressor 105 via a multiplexor 111. Similarly, information may be transferred to the main memory 103 from the processor data bus 108 to the write buffer and then either through or around the compressor 104 via a multiplexor 112.
The main memory 103 is typically constructed of synchronous dynamic random access memory (SDRAM) with access controlled by a memory controller 106. Scrub control hardware within the memory controller can periodically and sequentially read and write SDRAM content through error detection and correction logic for the purpose of detecting and correcting bit errors that tend to accumulate in the SDRAM. Addresses appearing on the processor address bus 107 are known as Real Addresses, and are understood and known to the programming environment. Addresses appearing on the main memory address bus 109 are known as Physical Addresses, and are used and relevant only between the memory controller and main memory SDRAM. Memory Management Unit (MMU) hardware within the memory controller 106 is used to translate the real processor addresses to the virtual physical address space. This translation provides a means to allocate the physical memory in small increments for the purpose of efficiently storing and retrieving compressed and hence, variable size information.
The compressor 104 operates on a fixed size block of information, say 1024 bytes, by locating and replacing repeated byte strings within the block with a pointer to the first instance of a given string, and encoding the result according to a protocol. This process occurs through a byte-wise compare over a fixed length and is paced by a sequence counter, resulting in a constant completion time. The post process output block ranges from just a few bytes to the original block size, when the compressor could not sufficiently reduce the starting block size to warrant compressing at all. The decompressor 105 functions by reversing the compressor operation by decoding resultant compressor output block to reconstruct the original information block by inserting byte strings back into the block at the position indicated by the noted pointers. Even in the very best circumstances, the compressor is generally capable of only xc2xc-xc2xd the data rate bandwidth of the surrounding system. The compression and decompression processes are naturally linear and serial too, implying quite lengthy memory access latencies through the hardware.
Referring to FIG. 2, prior art for partitioning the main memory is shown 200. The main memory 205 is a logical entity because it includes the processor(s) information as well as all the required data structures necessary to access said information. The logical main memory 205 is physically partitioned from the physical memory address space 206. In many cases, the main memory partition 205 is smaller than the available physical memory to provide a separate region to serve as a cache with either an integral directory, or one that is implemented externally 212. It should be noted that when implemented, the cache storage may be implemented as a region 201 of the physical memory 206, a managed quantity of uncompressed sectors, or as a separate storage array that may be directly accessed by the processor buses 107 and 108. In any case, when implemented, the cache controller will request accesses to the main memory in a similar manner as a processor would if the cache were not present.
The logical main memory 205 is partitioned into the sector translation table 202, with the remaining memory being allocated to sector storage 203 which may contain compressed or uncompressed information, free sector pointers, or any other information as long as it is organized into sectors. The sector translation table region size varies in proportion to the real address space size which is defined by a programmable register within the system. Particularly, equation 1) governs the translation of the sector translation table region size as follows:                               sector_translation          ⁢          _table          ⁢          _size                =                                                            real                ⁢                                  xe2x80x83                                ⁢                memory                ⁢                                  xe2x80x83                                ⁢                size                                            compression_block                ⁢                _size                                      ·            Translation_table                    ⁢          _entry          ⁢          _size                                    (        1        )            
Each entry is directly mapped to a fixed address range in the processor""s real address space, the request address being governed in accordance with equation 2) as follows:                               sector_translation          ⁢          _table          ⁢          _entry          ⁢          _address                =                                                                              real                  ⁢                                      xe2x80x83                                    ⁢                  address                                                  compression_block                  ⁢                  _size                                            ·              translation_table                        ⁢            _entry            ⁢            _size                    +          offset_size                                    (        2        )            
For example, a mapping may employ a 16 byte translation table entry to relocate a 1024 byte real addressed compression block, allocated as a quantity 256 byte sectors, each located at the physical memory address indicated by a 25-bit pointer stored within the table entry. The entry also contains attribute bits 208 that indicate the number of sector pointers that are valid, size, and possibly other information. Every real address reference to the main memory causes the memory controller to reference the translation table entry 207 corresponding to the real address block containing the request address 210. For read requests, the MMU decodes the attribute bits 208, extracts the valid pointer(s) 209 and requests the memory controller to read the information located at the indicated sectors 204 from the main memory sectored region 203. Similarly, write requests result in the MMU and memory controller performing the same actions, except information is written to the main memory.
However, if a write request requires more sectors than are already valid in the translation table entry, then additional sectors need to be assigned to the table entry before the write may commence. Sectors are generally allocated from a list of unused sectors that is dynamically maintained as a stack or linked list of pointers stored in unused sectors. There are many possible variations on this translation scheme, but all involve a region of main memory mapped as a sector translation table and a region of memory mapped as sectors. Storage of these data structures in the SDRAM based main memory provides the highest performance at the lowest cost, as well as ease of reverting the memory system into a typical direct mapped memory without compression and translation.
It is highly desirable to provide redundant main memory for the purpose of having a system be tolerant of a memory failure, as well as the capability for memory removal and replacement without interruption to application or operating system software operation. Architectures with these attributes are generally cost prohibitive for application in all but a few select niches. One architecture of this type is disclosed in Fault-Tolerant Computer System Design, by Dhiraj K. Pradhan (Prentice Hall), 1996, pp 15-18. Therefore, the need and opportunity has arisen for an improved architecture and method of data management in a processing memory system, to provide a highly reliable and maintainable main memory array, without significant cost or complexity.
It is an object of the invention to provide a processing system having a highly reliable and maintainable main memory, without the added cost normally incurred to incorporate redundant memory, for the purpose of tolerating and repairing faults within the main memory without interruption of application or operating system software operation.
It is a further object of the invention to provide an architecture, method and apparatus to provide a compressed data memory system having a main memory array that is configurable as a duplex, where identical content is maintained within each memory bank, such that any uncorrectable data error detected upon read access to a given bank, may be reread from the other bank with the intent of receiving data without error. Operational modes may be selected to permit either memory bank to be configured as a back-up, to permit physical removal and replacement of the bank, and for re-initialization and synchronization of the memory state for the purpose of regaining use of the memory. The cost of duplicating the memory is balanced by the savings from compressing the memory content, thereby achieving the high reliability function at a negligible cost.
According to the invention, a conventional SDRAM storage array is partitionable into two identical banks, comprised of user replaceable entities containing SDRAM with electrically isolated logic interfaces. All activity may be configured to occur concurrently to maintain xe2x80x9clock-stepxe2x80x9d synchronization between the two banks. Although memory read accesses always occur at both banks, an electrical isolation mechanism provides a means for the memory controller to selectively receive data from only one of the two memory banks, known as the primary bank, whereas the xe2x80x9cignoredxe2x80x9d bank is known as the back-up bank. However, write accesses always occur at both banks.
The conventional memory controller functions are designed with special consideration for duplex memory operation, including: A memory scrub controller mode to immediately scrub the entire memory address space by reading and then writing the content back for the purpose of initializing a back-up memory bank with the content from the primary bank. Further, the scrub controller alternates normal memory scrub read access between the two banks to insure the back-up bank has not accumulated any content errors. Lastly, the memory controller can be configured to fail-over to the back-up bank from the primary bank, upon detection of an uncorrectable error from the ECC in the data read path. The fail-over process involves swapping the bank configuration (back-up bank becomes primary bank and vice versa), and reissuing the read operation to receive the reply data from the new primary bank. Several xe2x80x9cduplexxe2x80x9d modes exist, permitting manual selection, automatic fail-over trip event, or automatic fail-over toggle event.